| Pin | Name |
| 1 | Vdd (3.3V) |
| 2 | PHI |
| 3 | /WR |
| 4 | /RD |
| 5 | /CS |
| 6 | AD0 |
| 7 | AD1 |
| 8 | AD2 |
| 9 | AD3 |
| 10 | AD4 |
| 11 | AD5 |
| 12 | AD6 |
| 13 | AD7 |
| 14 | AD8 |
| 15 | AD9 |
| 16 | AD10 |
| 17 | AD11 |
| 18 | AD12 |
| 19 | AD13 |
| 20 | AD14 |
| 21 | AD15 |
| 22 | A16 |
| 23 | A17 |
| 24 | A18 |
| 25 | A19 |
| 26 | A20 |
| 27 | A21 |
| 28 | A22 |
| 29 | A23 |
| 30 | /CS2 |
| 31 | IRQ |
| 32 | GND |
PHI is a programmable clock output (disabled by default, the selectable frequencies vary between the DS and GBA, see WAIT_CR)
During 'compatible' mode transfers (/CS2), AD0..AD15 are instead A0..A15, and A16..A23 serve as D0..D7.
Multiplexed bus accesses can be either sequential or non-sequential.
- Non-sequential reads are done by asserting the low 16 bits of the desired address on AD0..AD15, and taking /CS low, which will latch the counter. The actual data fetch is the same as a sequential read.
- Sequential reads are done by strobing /RD low: data will be output on AD0..AD15 and should be valid on the rising edge of /RD.
A16..A23 must be valid at all times, since the latchable up-counter is only 16 bits wide. The counter is clocked on each rising edge of /RD.
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