Everything on this page is ARM7 only
Fixme: mis-filed stuff about R_CR
R0_CR (0x04000138)
c1fc (80ff=80ff, behaves like R cr reg)
R2_CR (0x04000136) reads 007f, can't force any bits (see key info) (R2 because it was the 3rd discovered, rename!)
R1_CR (0x04000138) retains ff7b
The RTC is wired to the second general purpose I/O port on the ARM7 (0x04000138:16):
| bit | name |
| 3 | unknown/un-used (always input) |
| 2 | CS (active high chip select) |
| 1 | SCK (data clock) |
| 0 | SIO (data pin) |
Data written from the DS to the RTC should be valid on the rising edge of SCK, and data read back from the RTC to the DS should be sampled on the falling edge of SCK (i.e. just before setting SCK low, after the delay).
0x60: Write STATUS_REG1
0x62: Write STATUS_REG2
0x64: Write DATA_REG1
0x66: Write DATA_REG2
0x68: Write INT_REG1
0x6A: Write INT_REG2
0x6C: Write CLOCK_ADJUST_REG
0x6E: Write FREE_REG
Time data:
byte year; // year (0..99)
byte month; // month (1..12)
byte day; // day (1..(28..31))
byte week; // day of week (0..6)
byte hour; // hour of day (0..23 or 0..11), bit 6 is PM/AM
byte minute; // minute (0..59)
byte second; // second (0..59)
The data sent to/from the RTC must be in BCD format! LSB first.
The epoch for the year returned is 2000 (i.e. for 2005, it would return 5).
Interrupt mode:
| 32kE | INT1AE | INT1ME | INT1FE | Interrupt conditions |
| 0 | 0 | 0 | 0 | No interrupt |
| 0 | x | 0 | 1 | Selected frequency steady interrupt |
| 0 | x | 1 | 0 | Once a minute edge interrupt |
| 0 | 0 | 1 | 1 | Once a minute steady interrupt 1 (50% duty) |
| 0 | 1 | 0 | 0 | Alarm interrupt |
| 0 | 1 | 1 | 1 | Once a minute steady interrupt 2 |
| 1 | x | x | x | 32 kHZ output |