The ARM7 has a SPI (Serial Peripheral Interface) bus with three attached devices (and capable of selecting one of four devices). There is a control register (SERIAL_CR) and a data register (SERIAL_DATA).
These aren't unknown, I'm certain what they are, just not certain of the bits inside (need to piece together the firmware load and metroid touch screen writes, and find out what controls the CS lines for the various SPI devices)
Registers
| 0x040001C0:16 | SERIAL_CR |
| 0x040001C2:16 | SERIAL_DATA |
SERIAL_CR contents
| 15 | R/W | enable |
| 14 | R/W | irq on completion |
| 13..12 | R | 00 |
| 11 | R/W | /last_transmission |
| 10 | R/W | 0: 8 bit mode, 1: 16 bit mode |
| 9..8 | R/W | device selection |
| 7 | R | busy flag |
| 6..2 | R | 00000 |
| 1..0 | R/W | Clock rate (00: 4 MHz, 01: 2 MHz, 10: 1 MHz, 11: 512 KHz) |
As with other hardware, the irq generation is enabled here, but is also gated by the IE register (see Interrupts for more details).
Devices:
SPI is a synchronous clocked protocol: for every clock, a single bit of data is shifted out to the slave, and one shifted into the master, usually using the same physical register. In the DS, writing to the SERIAL_DATA register actually starts the transfer, and the returned value is available in SERIAL_DATA once the busy flag goes low in SERIAL_CR.
Code defining registers and fields:
#define SERIAL_CR (*(vuint16*)0x040001C0)
#define SERIAL_DATA (*(vuint16*)0x040001C2)
#define SPI_ENABLE (1<<15)
#define SPI_IRQ (1<<14)
#define SPI_BUSY (1<<7)
#define SPI_BAUD_4MHZ (0<<0)
#define SPI_BAUD_2MHZ (1<<0)
#define SPI_BAUD_1MHZ (2<<0)
#define SPI_BAUD_512KHZ (3<<0)
#define SPI_BYTE_MODE (0<<10)
#define SPI_HWORD_MODE (1<<10)
#define SPI_NOT_LAST (1 << 11)
#define SPI_DEVICE_POWER (0 << 8)
#define SPI_DEVICE_FIRMWARE (1 << 8)
#define SPI_DEVICE_TOUCH (2 << 8)